JIFFYDOS IECOUT (and SAVE)
C64-IECOUT & -SAVE ( = 1541-IECIN & -SAVE)
(for JD-databytes & JD-SAVE)
eddd bit $94 flag for IECOUT byte in buffer
eddf bmi $ede6 b.i.there is a byte in buffer
ede1 sec
ede2 ror $94 sets bit 7 = 1 = flag for byte in buffer
ede4 bne $edeb branches allways
--------------------
ede6 pha saves actual IECOUT byte
ede7 *jsr $fbfe transmits old IECOUT byte from buffer to floppy
edea pha restores actual IECOUT byte
edeb sta $95 stores in IECOUT buffer
edee rts
------------------------------------------------------------------------------
fbfe *sei prevents IRQs
fbff *bit $a3 JD IEC status byte (and EOI-flag)
fc01 *bvc $fc14 b.i. bit 6 = 0 = CBM IEC bus routines
fc03 *lda $d015 sprite register of VIC (=JD-IECOUT)
fc06 *beq $fc27 b.i. all sprites are off
fc08 *pha save sprite register to stack
fc09 *jsr $f0d8
====================
f0d8 *lda #$00
f0da *sta $d015 switch off all sprites
f0dd *adc #$01 2
f0df *bne f0dd 3 (2+3)*250=1250uS delay
f0e1 *rts
====================
fc0c *jsr $fc27 JD-IECOUT
fc0f *pla restores sprite register
fc10 *sta $d015 -"-
fc13 *rts
--------------------
fc14 *lda $a3 EOI-/JDstatus-byte
fc16 *cmp #$a0 %10100000 = after sec & ror$a3 = at sending of EOI
fc18 *bcs $fc03 b.i. JD IEC routines (at EOI)
fc1a *jmp $ed40 to CBM IEC bus routines
====================
fc24 *cli allows IRQs
fc25 *clc flag for ok (but often even at errors cleared)
fc26 *rts (end of JD-IECOUT)
-------------------- DC
fc27 *txa AL
fc28 *pha saves x register TO
fc29 *lda $95 IECOUT byte AC
fc2b *and #$f0 mascs high nibble K
fc2d *pha saves high nibble to stack
fc2e *lda $95 IECOUT byte
fc30 *and #$0f mascs low nibble first letter=data-out I -
fc32 *tax low nibble to x second letter=clock-out A-
fc33 *lda $dd00 4 reads bus (41:fbd8) lda $dd00 IA-
- IA-
- IA-
- IA-
fc36 *bpl $fc33 2/3 waits until 1541 sets data = inactive bpl $fc33 IA-
- IA-
fc38 *and #$07 2 mascs bit 2-0 =pin M of userport & VIC bank and #$07 IA-
- IA-
fc3a *sta $95 3 saves pinM&VICbank (stores it to IECOUTbyte) sta $95 IA-
- IA-
- IA-
fc3c *sec 2 sec IA-
- IA-
fc3d *lda $d012 4 VIC rasterbar lda $d012 IA-
- IA-
- IA-
- IA-
fc40 *sbc $d011 4 bit 2-0 = vertical softscroll register sbc $d011 IA-
- IA-
- IA-
- IA-
fc43 *and #$07 2 mascs bit 2-0, that 8 rasterbars remain and #$07 IA-
- IA-
fc45 *cmp #$06 2 cmp #$06 IA-
- IA-
fc47 *bcs $fc3d 2/3 b.i. too few time until next badline bcs $fc3d IA-
- IA-
fc49 *lda $95 3 (bus port byte) lda $95 IA-
- IA-
- IA-
fc4b *sta $dd00 4 data=inactive,clock=inactive,ATN=inactive sta $dd00 IA-
- (41:fbdb) IA-
- IA-
- put here 1541-paper-arrow(early/late)----------II)
fc4e *pla 4 high nibble of IECOUT byte pla II-
- II-
- II-
- II-
fc4f *ora $95 3 restores pin M & VIC-bank ora $95 II-
- II-
- II-
fc51 *sta $dd00 4 bit5-)data-out, bit4-)clock-out (41:fbe2) sta $dd00 II-
- II-
- II-
- ----54)
fc54 *lsr 2 lsr 54-
- 54-
fc55 *lsr 2 lsr 54-
- 54-
fc56 *and #$f0 2 masks off ATN, pin M, VIC bank and #$f0 54-
- 54-
fc58 *ora $95 3 restores pin M & VIC bank ora $95 54-
- 54-
- 54-
fc5a *sta $dd00 4 bit7-)data-out, bit6-)clock-out (41:fbe8) sta $dd00 54-
- 54-
- 54-
- ----76)
fc5d *lda $fc8a,x 4 table of low nibbles lda $fc8a,x 76-
- 76-
- 76-
- 76-
fc60 *ora $95 3 restores pin M & VIC-bank ora $95 76-
- 76-
- 76-
fc62 *sta $dd00 4 bit1-)data-out, bit3-)clock-out (41:fbf0) sta $dd00 76-
- 76-
- 76-
- ----13)
fc65 *lsr 2 lsr 13-
- 13-
fc66 *lsr 2 lsr 13-
- 13-
fc67 *and #$f0 2 masks off ATN, pin M, VIC bank and #$f0 13-
- 13-
fc69 *ora $95 3 restores pin M & VIC bank ora $95 13-
- 13-
- 13-
fc6b *sta $dd00 4 bit0-)data-out, bit2-)clock-out (41:fbf6) sta $dd00 13-
- 13-
- 13-
- ----02)
fc6e *and #$0f 2 (data=inactive,clock=inactive) and #$0f 02-
- 02-
fc70 *bit $a3 3 flag for EOI bit $a3 02-
- 02-
- 02-
fc72 *bmi $fc76 2/3 b.i. EOI bmi $fc76 02-
- 02-
fc74 *ora #$10 2 (clock=active) ora #$40 02-
- 02-
fc76 *sta $dd00 4 data=I clock=I (noEOI) / A (EOI) (41:fc00) sta $dd00 02-
- 02-
- 02-
- ----I?)
fc79 *pla 4 pla I?-
- I?-
- I?-
- I?-
fc7a *tax 2 restores x tax I?-
- I?-
fc7b *lda $95 3 restores pin M & VIC-bank lda $95 I?-
- I?-
- I?-
fc7d *ora #$10 2 (clock=active) ora #$10 I?-
- I?-
fc7f *sta $dd00 4 clock=active sta $dd00 I?-
- I?-
- I?-
- ----IA)
fc82 *bit $dd00 4 reads bus bit $dd00 IA-
- IA-
- IA-
- ----IA)
fc85 *bpl $fc24 b.i.1541 sets data = active
fc87 *jmp $edb0 time out error
DC
------------------------------------------------------------------------------
fc8a 00 80 20 a0 40 c0 60 e0 10 90 30 b0 50 d0 70 f0
==============================================================================
==============================================================================
1541-IECIN & -SAVE ( = C64-IECOUT & -SAVE)
(for JD-databytes & JD-SAVE)
DC
-A first letter=data-out
- I second letter=clock-out
ea2e
....
ea44 *jsr $fbcc IECIN
====================
====================
fbcc *lda $98 JD-IEC satus byte
fbce *bne $fbd3 b.i. JD-IEC bus routines
fbd0 *jmp $e9c9 CBM-IEC bus routines
--------------------
-AI fbd3 *lda $1800 reads bus
-AI fbd6 *and #$04
-AI fbd8 *sta $1800 4 data=inactive, clock=inactive, ATNackn=inactive
-AI a=#00 if C64 sets clock=inactive (=error)
-AI a=#04 if C64 sets clock=active (=ok) (64:fc36)
-II
-II
-II
-II
-II
-II
-II
-II
-II
-II 1541 waits some loops
-II until C64 calculates its badline
-II
-II
-II
-II
-II
-II
-II
-II
-II fbdb *bit $1800 4 reads bus (64:fc4b)
-II
-II for 0.1uS
(II-----------put here C64-paper-arrow (late). Here if 41 failed D=I from C64
-II fbde *bne $fbdb 2/3 waits until C64 sets clock = inactive 0us
-II late: 41 failes D=I from C64 for 0.1uS
-II =)branches 3uS
-II fbdb *bit $1800 4 reads bus (64:fc4b)
-II
-II exactly
(II-----------put here C64-paper-arrow (early). Here if 41 found D=I from C64
-II fbde *bne $fbdb 2/3 waits until C64 sets clock = inactive 0us
-II early: 41 found D=I from C64 exactly =) no branch 2uS
-II fbe0 *pha 3 delay
-II
-II
-II fbe1 *pla 4 delay
-II
-II
-II
-II fbe2 *lda $1800 4 reads bus (64:fc51)
-II
-II C64 1541 C64 1541
(II---- bit5=data-)bit0 bit4=clock-)bit2 13 20us
-II fbe5 *asl 2 bit0-)bit1 bit2-)bit3 0d 14
-II
-II fbe6 *pha 3 delay
-II
-II
-II fbe7 *pla 4 delay
-II
-II
-II
-II fbe8 *ora $1800 4 bus (64:fc54)
-II
-II C64 1541 C64 1541
(II---- bit7=data-)bit0 bit6=clock-)bit2 26 33us
-II fbeb *and #$0f 2 mascs bit 3-0 1a 21
-II
-II fbed *tax =highnibble of C64-IECOUT byte
-II
-II fbee *ldy $7a 3 =#$00 (flag for TALK)
-II (not ldy #$00 because of timing: 3uS instaed of 2uS)?
-II
-II fbf0 *lda $1800 4 reads bus (64:fc62)
-II
-II C64 1541 C64 1541
(II---- bit1=data-)bit0 bit3=clock-)bit2 37 44us
-II fbf3 *asl 2 bit0-)bit1 bit2-)bit3 25 2c
-II
-II fbf4 *pha 3 delay
-II
-II
-II fbf5 *pla 4 delay
-II
-II
-II
-II fbf6 *ora $1800 4 bus (64:fc68)
-II
-II C64 1541 C64 1541 50 57us
(II---- bit0=data-)bit0 bit2=clock-)bit2 25 2c
-II fbf9 *and #$0f 2 mascs bit 3-0
-II
-II fbfb *ora $fc13,x 4 table for highnibble
-II
-II
-II
-II fbfe *sta $85 3 1541 IECIN byte
-II
-II
-II fc00 *lda 1800 4 reads bus (64:fc76)
-II
-II
(II---- 63 70us
-II fc03 *ora #$02 2 3f 46
-II
-II fc05 *sta $1800 4 data = active (64:fc82)
-II
-II
(AI----
-AI fc08 *bmi $fbd0 2/4 b.i. C64 sets ATN = active
-AI fc0a *and #$04 mascs clock in bit
-AI fc0c *bne $fc10 b.i. C64 sets clock=active (=no EOI)
-AI fc0e *sty $f8 #$00-)$f8 =flag for EOI
-AI fc10 *lda $85 transmitted C64-IECOUT byte (=1541-IECIN byte)
-AI fc12 *rts
DC
------------------------------------------------------------------------------
fc13 00 80 20 a0 40 c0 60 e0 10 90 30 b0 50 d0 70 f0
==============================================================================
==============================================================================
Put the right margin of the C64-paper-sheet to the left margin of the 1541-
paper-sheet, it fits and shows the timing.
Every line is 1uS.
You can move the sheets seven lines up and down, depending on the 7uS
waiting-loop.
The 1541 waiting loop at fbde (for C64 is ready) is 7uS long. =) The tolerance
must be greater than 7uS (it is minimum 11uS).
Put the C64-arrow at fc4b to one of the two 1541-arrows (late/early) at fbdb.
Late: When the 1541 reads the bus, the clock line is still set to active by
the C64. The C64 sets the clock line to inactive an extremely short time later
(f.e. 0.1uS), so the 1541 must wait one complete loop (7uS). So the 1541
leaves the loop 7uS later than the C64 inactivates clock.
Early: The 1541 reads the bus exactly in the moment when the C64 sets the
clock line to inactive. So the 1541 doesn't wait but continues at once. So the
1541 leaves the loop 0uS later than the C64 inactivates clock.
C64-time from load-VIC-rasterbar-register to last-action-at-bus: 93uS
----------------------------------------------------------------------
2000/01/30
Near Letter Quantity
Jochen Adler
NLQ@gmx.de
http://home.t-online.de/home/dadler/
----------------------------------------------------------------------
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